With development of the semiconductor structure manufacturing technology, integrated circuits with better performance and more powerful functions require greater element density, and the size of the elements and the spacing among the elements need to be further downscaled. As a result, the technique of lithography is facing more rigid requirements and challenges in the process of manufacturing semiconductor structures. Particularly, in manufacturing chips of static random access memories (SRAM), the Line-and-Cut dual patterning technology is usually applied to form gates in semiconductor structures. Here below, application of this technology in the prior art is to be described in conjunction with FIG. 1 to FIG. 4.
FIG. 1 illustrates part of a semiconductor structure with gates formed by way of Line-and-Cut technology in the prior art. As shown in FIG. 1, first, a substrate 10 with a gate material layer formed thereon in advance is overlaid with a photoresist layer 11; then, the photoresist layer 11 is exposed and developed with a mask in order to pattern the photoresist layer 11 whereby a linear pattern, which corresponds to a gate line pattern, is outlined. Next, the gate layer is etched to form gate lines 12 (the structure shown in FIG. 1 is the structure formed after the gate layer is already etched). With reference to FIG. 2, which illustrate a cross-sectional view of the semiconductor structure shown in FIG. 1 in the A-A direction, the gate lines 12 are laid out on the substrate 10, and the upper plane of the gate lines are overlaid with the photoresist layer 11. Next, with reference to FIG. 3, another exposure process is performed with a cut mask in order to form openings 13 on the photoresist layer 11, wherein the openings 13 expose the gate lines 12. The gate lines 12 are etched via the openings 13, by which the gate lines 12 can be cut. With reference to FIG. 4, in which the photoresist 11 is already removed, after the gate lines 12 are etched via the openings 13, the photoresist 11 and part of the gate lines 12 are removed to form cuts 16, wherein the gate lines 12 are cut into electrically isolated gates by the cuts 16, for example, the electrically isolated gates 14 and 15 shown in FIG. 4.
However, aforementioned traditional process is subject to following shortcomings: first, the above technique of lithography is subject to such rigid requirements that the distance between ends has to be extremely precise. Particularly, it becomes increasingly difficult to implement such a gate line patterning process along with development of downscaling size in devices. In order to increase integration density, manufacturing of the cut mask, which is used in formation of cuts that are required to be slim enough, would also become increasingly difficult. Additionally, application of the abovementioned technique would become more complicated in gate replacement and high K dielectric processes. A process of sidewall spacer dual patterning may be required in a technical node below 22 nm.
For example, the width of the openings 13 in the direction of gate width can be as small as 30 nm˜50 nm because of limitations from technical conditions in the prior art, consequently, the width of cuts 16, which are formed via the openings 13, in the direction of gate width is also in the range of 30 nm˜50 nm. In other words, the minimal distance between the ends of two neighbouring electrically isolated gates that are located on the same line is 30 nm. With further development of semiconductor manufacturing technology, for example, in the 45 nm process, the distance between the ends of two neighbouring electrically isolated gates located on the same line is desired to be further reduced for the purpose of achieving a higher integration density. However, due to limitations of current technical conditions, no process in the prior art is capable of further reducing the distance between the ends of two neighbouring electrically isolated gates located on the same line to below 30 nm, which therefore becomes an issue that needs to be solved in order to increase integration density.
In addition, in the subsequent processes, sidewall spacers that surround the gates usually have to be formed on both sides of the electrically isolated gates. Due to the existence of the cuts 16, at the time of forming sidewall spacers, material for forming sidewall spacers, on the one hand, deposits on both sides of the gates and, on the other hand, flows into the cuts 16. As the cuts 16 are very narrow, the sidewall spacer material is prone to form defects such as hallows in the cuts, which is adverse to the subsequent processing of semiconductor devices, particularly, short-circuit is prone to occur at the time of forming metal plugs subsequently. In addition, if the gates are dummy gates, then these hallows would cause problems such as short circuit at the time of forming replacement gates subsequently. This undermines performance and stability of semiconductor devices.